As shown in FIG. 6, a typical capacitive element CD in a semiconductor consists of a plurality of unit electrodes (not shown) in capacitive element area CDA and a common electrode (not shown) facing the capacitive element area through an insulation layer (not shown). The unit capacitor electrodes are arranged two-dimensionally to form one, or a plurality of, capacitive element(s) with predetermined capacitance. Each unit electrode is linked to main conductor lines L1 and L2 through lead lines UL1 and UL2 respectively; and the common electrodes are linked to main conductor line L3 through lead lines OL. These conductor lines generally lead in the direction of the capacitive element with spacing between lines minimized to reduce interconnection space and achieve a compact semiconductor.
However, in such an interconnection layout structure, parasitic capacitance is generated between L3 and L1 or L2. This parasitic capacitance reduces the ability to accurately calculate the capacitance of the capacitive element(s) especially when a plurality of capacitive elements are arrayed, as above, because the parasitic capacitance value differs for every capacitive element, in that the parasitic capacitance between L1 and L3 and that between L2 and L3 are not generally equal. Consequently, parasitic capacitance causes output errors.